1. Field of the Invention
The present invention relates to an audio processing integrated circuit. More particularly, the present invention relates to an audio processing integrated circuit including a noise suppressing circuit and operating method.
2. Description of the Related Art
Popping and clicking sounds are unwanted, noisy, audible sounds produced by audio circuits that are connected to sound generating sources such as speakers and headphones. Application of power to an integrated circuit connected to a sound generating source for driving audio signals is one condition that produces pops and clicks. The noise results from a large increase in voltage at the output terminals of the integrated circuit from near zero volts before power is applied to a nominal voltage when the integrated circuit is powered.
Another condition that produces pops and clicks is playback of signal samples encoded in a format different from the default format of the integrated circuit. For example, an integrated circuit using a 16-bit signed format as the default format generates clicks when samples in a different format are received. The pops and clicks result because, when the playback path is initialized or deactivated, a sample formatting block in the integrated circuit is initialized to the default state that is set to receive 16-bit signed format samples.
A typical integrated circuit includes a first-in-first-out (FIFO) buffer that feeds data to the sample formatting block. In the default condition, the FIFO output latches are reset to zero so that zero samples are transferred to the sample formatting block. In the default condition, when the play path of the integrated circuit is enabled, the sample formatting block reads zeroes from the FIFO and generates zeroes that maintain the analog output signal at mid-scale. Consequently, the audio output signal is silent and no audible popping or clicking results.
In some circumstances, a programmer may select an alternative data format other than the default 16-bit signed format. For example, a programmer may select processing of 8-bit samples. Since the default condition of the FIFO output latches and sample formatting block are initialized to zero, the sample formatting block translates the 8-bit zeroes to a non-zero signed value based on the programmed 8-bit format (unsigned, xcexc-law, or A-law). Table I illustrates the correspondence between 8-bit zeroes and 16-bit values:
A result of the formatting discrepancy after 8-bit playback enable is the generation of a transient in the analog output signal. The transient is expressed acoustically as an audible pop or click. An example of a transient is shown in FIG. 1, a graph which illustrates an analog trace resulting from the playing of 8-bit zeroes. In the example, the sample formatting block is programmed for the 8-bit unsigned format. After play is enabled, the FIFO is written and filled with hexadecimal 80H values which are equivalent to an analog midscale value, in one example, VREF=2.0 volts. As shown in FIG. 1, the analog output signal forms a spike to the negative full-scale value as the initial data zeroes in the FIFO are read. Once the hexadecimal 80H values from the FIFO are read, the analog output signal returns to the midscale value.
One solution to the problem of transients resulting from data format changes is achieved by initializing the FIFO to correct values based on the programmed 8-bit format. Such initialization requires additional complex circuit in the FIFO so that the FIFO presents the proper 8-bit midscale value after initialization. Unfortunately the complex FIFO circuit consumes a larger integrated circuit area than is desired.
What is needed is a simple circuit and operating technique that eliminate format-dependent signal transients and resultant pops and clicks.
Transient signals resulting from format changes in a signal processing circuit that cause audible popping and clicking noises are simply and efficiently eliminated by disabling handling of data samples during changes between data formats.
The transient signals are eliminated in a signal processor circuit that includes a buffer for storing digital data samples and a circuit for eliminating format-dependent transients in a signal processor connected to the buffer. The digital data samples are selectively formatted in a plurality of data formats. The circuit for eliminating format-dependent transients includes a sample formatter connected to the buffer that receives digital data samples from the buffer and selectively modifies the digital data samples from a first data format to a second data format of the plurality of data formats. The circuit for eliminating format-dependent transients also includes an interpolator coupled to the sample formatter and a control logic connecting the sample formatter to the interpolator for disabling transfer of digital data samples from the sample formatter to the interpolator during changes between data formats, and otherwise enabling transfer.